The present invention relates to the control of data channel information in a device for the automatic in-circuit and/or functional digital testing of electronic components, and more particularly to a method for storing control data in a local memory of a data channel to substantially reduce the time required to load the data.
In a digital tester such as an in-circuit/functional electronic component tester of the type shown in U.S. Pat. No. 3,870,953 to Boatman et al, stimulus signals are applied to various accessable nodes on a printed circuit board and the response of individual components or groups of components on the board are measured at other nodes. The nature of the stimulus signals is such that they do not harm other components on the printed circuit board but they drive the node of the circuit under test sufficiently to overcome the influence of other components that might be connected to that node. In other digital testers for testing electronic components that are not connected to other circuits, e.g., individual IC's, or for functionally testing entire circuit boards through edge connectors, stimulus signals are similarly applied and responses are similarly measured, but the problems of harming other components and overcoming other signal levels are not present.
These various types of digital testers while differing significantly in the foregoing respects, do share a common problem with respect to time constraints, a problem addressed by the present invention. In particular, the time necessary to test an IC or a printed circuit board or each individual IC on a printed circuit board is a function of the speed with which the IC or board can be fully stimulated and measured for proper response to each stimulus. This problem may be understood more clearly through a discussion of a typical computer controlled in-circuit component tester of the type shown in the referenced Boatman et al patent.
In a computer controlled in-circuit tester, the stimulus signals are generated by a central control computer and applied to the nodes on the board through appropriate control and switching circuitry. The response of the tested electronic components to the stimulus signals can be fed directly to the control computer for evaluation, or can be received and processed by intermediate circuitry, and the results of the processing fed to the computer for final evaluation.
In some of the earliest versions of automatic test equipment of this type, the stimulus data generated by the computer was fed directly from the computer to the circuit nodes of the component being tested. However, the rate at which data can be transferred from the computer to the circuit under test (e.g., 1 MHz) is limited by the constraints of the software used in the computer. Consequently, the time necessary to thoroughly exercise a circuit, and particularly to test all components by in-circuit techniques, becomes excessively long as the length of test programs increase due to the advancing state of microelectronics and complexity of individual integrated circuit chips.
In order to reduce the time necessary to exercise a component or group of components in a circuit under test, automatic in-circuit test equipment has been provided with a local memory for each data channel in the tester as had previously been done in functional board testers and component testers. A typical data channel usually includes a driver/detector pair and a stimulus/response register in addition to the local memory. To conduct a test, the local memory is loaded with the stimulus vectors or test pattern and the expected response signals generated by the computer. Thereafter, the stored vectors are applied to the circuit under test through the data channels at a rate much faster than the rate at which they are originally read from the computer (e.g. 10-20 MHz). The ability to apply the test vectors to the circuit under test at this faster rate, coupled with the fact that various data channels can be operated simultaneously rather than sequentially by virtue of their local memory, substantially increases the speed with which a circuit can be thoroughly tested. A recent example of an in-circuit tester that incorporates local memory for each data channel is disclosed in U.S. Pat. No. 4,216,539.
With the increasing development and popularity of large scale integrated (LSI) and very large scale integrated (VLSI) circuit chips, the number of circuits and the complexity of functions performed within an individual chip require complex testing programs that play an important role in the rate at which circuits incorporating such chips can be thoroughly exercised. In a production environment in which thousands of circuit boards each containing a number of individual circuits must be tested daily, the throughput capabilities of the tester, i.e., the time required to thoroughly test an individual circuit board, becomes a very important practical consideration. Consequently, it becomes desirable to increase the throughput rate of automatic testers even further.
In an article entitled "Functional and In-Circuit Testing Team Up To Tackle VLSI In the '80s" by Peter Hansen, appearing in Electronics Magazine, Apr. 21, 1981, pp. 189-195, the author notes that the effective test rate of a system is the sum of the time to load data in a local channel memory, the time during which the data is transferred between the test system and the circuit board under test, and the measurement time in which results are compared. As discussed previously, the use of a local memory for each data channel may substantially reduce the time required to exchange information between the test system and the circuit under test, so that for all practical purposes this time period is not a significant factor in computing the overall test rate.
If the software of the central control computer is used to analyze the response of the circuit under test to the applied stimulus signals, the measurement time in the test procedure can be excessive. However, as disclosed in the Hansen article, if the hardware associated with each of the individual channels is configured so that it is capable of analyzing the responses from the tested circuit as well as apply the stimulus signals, e.g., if each data channel includes a comparator all of the responses in each of the channels can be analyzed simultaneously, thereby reducing the measurement time to the point where it also is not a significant factor in the overall test rate.
Consequently, the time required to load test vectors from the central control computer to the local memories of the individual data channels is a significant factor in determining the speed capabilities of the test system, and represents the next area to be addressed in decreasing total throughput time. The reason that the loading time is excessively long in comparison with the other steps of the test procedure is the fact that in presently available systems, all of the memory points in the local memory must be addressed at the time the information is being fed from the central control computer to the memory. In a typical in-circuit tester, each local memory might have a depth of 1000 bits of information. If the tester contains 128 data channels multiplexed to accommodate 256 test pins, for example, it will be appreciated that the time to load the test vectors from the computer into the memories can be considerable. For example, in one type of tester, information relating to transitions that occur in the channel data is stored on a disk in the central control computer system. Information relating to two data transitions stored on the disk might represent 10 test vectors to be applied during a test wherein the first 5 vectors are the same signal and the last 5 vectors each comprise the same signal, for example. Thus, each piece of transition data stored on the disk must be appropriately expanded into the appropriate number of corresponding test vectors before they can be loaded into the local memory. The time necessary to perform the expansion operation and thereafter load the test vectors into all of the memory points renders the total loading time prohibitively long.
Accordingly, it is a general object of the present invention to decrease the amount of time necessary to load test vector information from a central control computer into the local memories for data channels in an automatic digital tester.
It is another object of the present invention to achieve this general objective by reducing the amount of information that is required to be loaded into the memory.
It is a further object of the present invention to provide a novel method and apparatus for controlling the flow of information from a local memory in a data channel such that each storage location in a local memory need not store data that is significant to the test procedure.
It is a particular object of the present invention to provide a novel local memory system for a digital tester that requires only the storage of channel vector transition information and control data relating to the validity of stored data to thereby significantly reduce the effective test rate of the tester.
The manner in which the present invention achieves these, as well as other, objects and advantages will be more fully explained with reference to particular examples of the prior art and implementations of the invention illustrated in the accompanying drawings and described in the following detailed description.